pccx Documentation

Welcome to the pccx (Parallel Compute Core eXecutor) documentation. pccx is a scalable NPU architecture for accelerating Transformer-based LLMs on edge devices. Select a section from the sidebar to begin.

Ecosystem

KV260 integration

github.com/pccxai/pccx-FPGA-NPU-LLM-kv260

KV260 + LLM application integration for the v002 line. Reusable IP-core sources live in pccx-v002; this repository owns board flow, driver handoff, and application wiring.

Current focus: Gemma-3N E4B @ W4A8KV4 remains an evidence-gated target. Token-rate, board-run, and timing-closure results are pending measured KV260 evidence (see Evidence). Everything else (v003 / Gemma-4 / Llama) lives on the Roadmap.

Every v002 RTL reference page on this site links back to the exact .sv file in that repository.

Open the pccx-FPGA-NPU-LLM-kv260 repository on GitHub

Documentation source

github.com/pccxai/pccx — the Sphinx project powering this site.

Open the pccx documentation repository on GitHub

Author portfolio

hkimw.github.io/hkimw — blog, other projects, about.

Open the hkimw portfolio site

The public pccx-v003 repository now serves as the v003 IP-core planning package. It is an evidence-gated planning package, not a stable RTL release. The earlier pccx-LLM-v003 feeder is superseded / retired and is no longer an active public track; new reusable v003 LLM material belongs under pccx-v003/LLM/. Board and model repositories consume v003 material only through explicit compatibility contracts.

Tooling & Lab

pccx-lab

CLI-first verification lab for pccx traces, reports, diagnostics, and workflow boundaries. GUI, IDE, launcher, and future MCP surfaces should reuse the same CLI / core boundary instead of duplicating logic.

Work in Progress

Source: github.com/pccxai/pccx-lab

Open the pccx-lab verification lab

Design rationale

Why pccx-lab is one repo, not five. Phase 1 split the monolith into a 10-crate Cargo workspace (core, reports, verification, authoring, evolve, remote, lsp, uvm_bridge, workflow_facade, ui/src-tauri).

Read the pccx-lab design rationale

Formal model — Sail

pccx is formally specified in Sail — the same ISA-semantics language used for RISC-V, Arm, CHERI, and Morello. The 64-bit / 4-bit-opcode v002 ISA lives under formal/sail/ in the RTL repo; each SystemVerilog typedef has a 1:1 Sail counterpart so width drift fails Sail’s type checker before it fails silicon.

Read the pccx Sail ISA model

Introduction

• pccx: Parallel Compute Core eXecutor
  • 1. Architecture Overview
  • 2. Key Technical Features
  • 3. Documentation
  • 4. License
  • 5. Ecosystem
• Quickstart
  • 0. What you get
  • 1. Prerequisites
  • 2. Clone all three repos
  • 3. One-command reproducer (Docker)
  • 4. Native path (no Docker)
  • 5. Board path (optional)
  • 6. Where to go next
  • Cite this page
• Evidence
  • Measured (reproducible)
  • Pending (board / synth)
  • Baselines (for future comparison)
  • How this page gets updated
  • Cite this page
• Repository boundaries
  • Repository roles
  • Placement rule
  • Naming red flags
• Roadmap
  • Now — v002.0: baseline integration on KV260
  • Next — v002.1: sparsity + speculative decoding stack
  • Later — v003.x: separate RTL repository (LLM line continued)
  • Parallel — vision-v001: CNN inference track on KV260
  • Family overview
  • Links

v002 Architecture

• pccx v002 Architecture

Target Hardware

• Devices

pccx-lab Handbook

• pccx-lab Handbook

Archive

• Archive

Toolchain Demos

• Toolchain Demos

Tools

• pccx-lab — Verification Lab