NPU Top-Level¶

RTL source on GitHub

SystemVerilog source documented on this page: hw/rtl/NPU_top.sv

NPU_top.sv is the top integration wrapper. It exposes:

S_AXIL_CTRL — AXI-Lite control (HPM port, 250 MHz)
S_AXI_HP{0,1}_WEIGHT — 128-bit weight streams for the GEMM systolic array
S_AXI_HP{2,3}_WEIGHT — 128-bit weight streams for the GEMV core
S_AXIS_ACP_FMAP / M_AXIS_ACP_RESULT — ACP feature-map input and result output

All four sub-cores (GEMM, GEMV, CVO, mem_dispatcher) are instantiated here and connected through the shared L2 cache bus.

Last verified against

Commit 773bd82 @ pccxai/pccx-FPGA-NPU-LLM-kv260 (2026-04-21).